The invention relates to an insulated gate field effect transistor structure and further to a method of manufacturing such a structure.
In an insulated gate field effect transistor (IGFET) structure, a semiconductor channel region between source and drain is controlled by a gate insulated from the channel. IGFET structures are generally implemented as Metal Oxide Semiconductor (MOS) structures.
A double diffused MOS (DMOS) structure may be used in which a long lateral path, known as the drift region, extends between drain and source diffusions. The drift region attenuates any high voltages applied between drain and source down to around 20 in the channel region controlled by the gate.
In order to maximise the voltage capability of the transistor, the drift region would ideally be long and or lightly doped. Unfortunately, these properties would mean that the drift region would contribute a relatively high resistance to the overall device when the transistor is on. To address this, it is known to dope the drift region with an appropriate doping profile and to choose its thickness such that the reversed bias junctions between the MOSFET channel and source and between the channel and the substrate deplete the entire drift region of charge carriers when the device is turned off. This creates a uniform electric field in the drift region when a large voltage is applied across the transistor when switched off, which maximises the breakdown voltage since there are no peaks in the electric field to initiate premature avalanche breakdown. The fully depleted drift region is said to be in a RESURF (reduced surface field) condition. In a RESURF structure, the full thickness of the drift region is depleted when the device is turned off.
A lateral MOS device using this technique is described in U.S. Pat. No. 5,412,241 to Merchant, assigned to Philips Electronics North America Corp. The device is illustrated in FIG. 1.
The device is a silicon on insulator (SOI) device having a layer of silicon 101 formed on a buried oxide layer 103 on a semiconductor substrate 105. Source 107 and drain 109 regions are formed in the silicon, and connected to source 108 and drain 110 contacts respectively.
A gate layer 111 is provided over part of the silicon layer 101 which forms a channel, separated from the channel by a gate oxide 112. The gate layer is connected to a gate contact 113. The gate controls conduction between source 107 and drain 109, as is well known.
Between the channel and the drain a drift region 119 is provided in the silicon layer 101 to allow large voltages (e.g. 100V or more) to be applied between source and drain. A large voltage applied across source and drain may be at least partially dropped in the drift region thus reducing the voltage dropped in the channel.
A field plate 115 is formed integrally with the gate layer 111 over the LOCOS oxide layer 114 and extends laterally over the drift region 119 in the silicon layer 101. When the device is turned off, the field plate depletes the drift region to provide a RESURF effect.
The drift region 119 is protected from the effects of an impinging electric field, such as may be caused by moisture or other charged contaminants on the surface of the wafer, by the field plate 115. Electric fields will terminate on the field plate 115.
Further, because the field plate is connected to the gate the drift region 119 may be depleted from the top which means that the device can be designed with a higher doping level in the drift region than would otherwise be possible. This means that the device of U.S. Pat. No. 5,412,241 can be made with a low on-resistance.
Such silicon on insulator device structures exhibit, by virtue of their structure, low values of the capacitance between gate and drain (Cgd) and the charge needed to be supplied through gate and drain to switch the device (Qgd). These low values of Cgd and Qgd give rise to rapid switching, i.e. a rapid response to changes in gate voltage.
However, there remains a need for fast switching, both in SOI devices and in other IGFET types.
IGFET devices are highly sensitive to excessive voltages. If too high a voltage is present between the gate and the channel the gate insulator may break down and destroy the device. Such high voltages may simply be present in the circuit in which the IGFET device is mounted or alternatively the voltage may be electrostatic. It is accordingly highly beneficial to provide suitable protection for the gate, known as electrostatic discharge protection.
According to the invention there is provided a field effect transistor structure comprising: a source and a drain laterally spaced in a body semiconductor layer; a channel and a drift region in the body semiconductor layer between the source and the drain; an oxide layer over the channel and the drift region; an upper semiconductor layer arranged over the oxide layer, wherein the upper semiconductor layer is doped to have a gate region arranged over the channel, a field plate region arranged over the drift region and at least one p-n junction forming at least one diode between the field plate region and the gate electrode region; and an electrical interconnection between the source region and the field plate to electrically connect the source region and the field plate.
The transistor structure thus provides at least one electrostatic protection diode in a simple structure that is convenient to manufacture. The diode or diodes provided in the structure according to the invention protect the gate from electrostatic discharge by virtue of Zener action. If too high a voltage is present between gate and source, the diode or diodes undergo reverse breakdown to allow current to flow between gate and source.
Moreover, the source-connected field plate acts as a Faraday screen between gate and drain so reducing Cgd and hence the charge needed to be applied through gate and drain. This decreases the switching time.
In contrast, the gate-connected field plate of U.S. Pat. No. 5,412,241 allows the drift region to be depleted by a suitable voltage on the gate and hence on the field plate. This prior art arrangement will normally increase Cgd rather than reduce it as in the present invention. Accordingly, the prior art arrangement will tend to increase switching time.
There is no need for fine patterning of the upper semiconductor layer itself, since it is the dopant masks that define the regions of the layer that form the field plate, gate electrode and diodes. It is also not necessary to form separate field plate and gate electrode layers, which might at first sight be thought necessary if a field plate not connected to the gate electrode were to be required. These features simplify manufacture.
The transistor structure is preferably formed to have a source and drain of a first conductivity type. The drift region may be of the same conductivity type but of lower doping, and the channel may be formed in a body region of opposite conductivity type. The first conductivity type may be n-type.
The p and n regions of the upper semiconductor layer preferably alternate to form at least one diode.
At least one pair of back to back diodes may be provided in the upper semiconductor layer between the gate and the field plate.
A plurality of back to back diodes may be provided to increase the maximum voltage between source and gate before breakdown occurs.
At first sight, it might appear that the increase in gate-source capacitance Cgs would counteract any benefit of the reduced Cgd. However, this is not generally the case. In conventional circuit arrangements, the Miller effect comes into play. The total input capacitance Cinput is given by the sum of Cgs and the Miller capacitance, CM=(1+gMRL)Cgd, where RL is the load resistance and gm the transconductance. This means that the switching speed may be dominated by the contribution from Cgd so that the device according to the invention generally has an improved switching speed.
The upper semiconductor layer including the gate electrode and the field plate may be fabricated from any convenient semiconducting material, such as polysilicon. The field plate may be doped n+or p+.
The drift region may be linearly graded, i.e. it may have a concentration of dopant that varies linearly decreasing away from the drain. This may result in an improved breakdown performance compared with a drift region of constant concentration.
The invention may be implemented in a SOI structure, with a substrate, a buried oxide layer on the substrate and the body semiconductor layer deposited on the buried oxide layer. Source, drain, channel and drift regions may be formed from implantations in the deposited body semiconductor layer. Such SOI structures offer advantages, such as intrinsically lower capacitance.
The oxide layer may include a LOCOS layer above the drift region and a gate oxide layer above the channel.
Preferably, the doping concentrations are such that the depletion region spreads throughout the drift region when the transistor is turned off, that is to say the transistor is a reduced surface field (RESURF) transistor. The depletion region may extend into the body and drain.
The invention also relates to method of manufacturing a field effect transistor including, in any order, the steps of: forming an oxide layer over a semiconductor body layer; depositing an upper semiconductor layer over the oxide layer; diffusing alternating p and n regions in the upper semiconductor layer to form a gate region, a field plate region and at least one p-n junction forming at least one diode between the field plate region and the gate region; diffusing source and drain diffusions to form source and drain in the semiconductor body layer; and depositing a metallisation layer defining a source contact connected to the source region and to the field plate region, a gate contact connected to the gate region and a drain contact connected to the drain region.
The method accordingly provides a simple method of manufacturing a semiconductor transistor structure with integral electrostatic discharge protection and a source-connected field plate.
The oxide layer over the drift region may be formed by local oxidation of silicon.